In the development of a leading end CMOS (Complementary MOS) device in which the size of the transistor is getting smaller, there have been problems of degradation of the drive current due to depletion in the gate electrode made of polysilicon (poly-Si) and increase in gate leak current due to reduction in thickness of the gate insulating film. To address these problems, a hybrid technology has been investigated, in which a metal gate electrode is used to prevent the depletion in the electrode and the gate leak current is reduced by using a high dielectric constant material for the gate insulating film to increase the physical film thickness.
As the material used for the metal gate electrode, pure metals, metal nitrides, silicide materials and the like have been investigated. In any of the cases, however, the threshold voltages (Vth) of the n-type MOS transistor (hereinafter referred to as “nMOS”) and the p-type MOS transistor (hereinafter referred to as “pMOS”) need to be set to appropriate values.
To achieve a Vth value smaller than or equal to ±0.5 eV in a CMOS transistor, the gate electrode in the nMOS needs to be made of the material having an effective work function smaller than or equal to the mid-gap of Si (4.6 eV), desirably smaller than or equal to 4.4 eV. Similarly, the gate electrode in the nMOS needs to be made of the material having an effective work function greater than or equal to the mid-gap of Si (4.6 eV), desirably greater than or equal to 4.8 eV.
To achieve the above requirements, there has been proposed a method for controlling the Vth values of the transistors by separately using silicide electrodes having the same metal composition but containing different impurities as the gate electrodes in the nMOS and pMOS (dual-metal gate technology). For example, International electron device meeting technical digest, 2002, p. 247 and International electron device meeting technical digest, 2003, p. 315 disclose devices using gate insulating films made of SiO2 and Ni silicide gate electrodes (P-doped NiSi and B-doped NiSi) obtained by silicidation of the entire poly-Si electrodes (polysilicon electrodes) into which impurities, such as P and B, are implanted, using Ni. These references state that the effective work function of each of the gate electrodes is modulated by 0.5 eV at the maximum. The disclosed technology is characterized in that a poly-Si electrode can be silicided after high-temperature heat treatment for activating impurities in the source/drain diffusion regions of the CMOS transistor. There is thus provided an advantage of being highly compatible with the CMOS process of related art.
Further, International electron device meeting technical digest, 2004, p. 91 proposes a technology for controlling the Vth values of the transistors by separately using Ni silicide electrodes having different compositions as the gate electrodes in the nMOS and pMOS. In this technology, an NiSi2 electrode or an NiSi electrode is used for the nMOS and an Ni3Si electrode is used for the pMOS so that the effective work function can be modulated by 0.4 eV at the maximum even on HfSiON, which is a high dielectric constant gate insulating film. This technology provides advantages of being highly compatible with the CMOS process of related art and being applicable to an HfSiON gate insulating film.
Further, a solution has been investigated to eliminate the problem of unintentional change of the composition of the NiSi electrode to a Ni-rich composition when the gate length of the semiconductor device is short. In the method described in Symposium on VLSI Technology technical digest, 2005, p. 72, a reaction is initiated between part of poly-Si, which later becomes the gate electrode, and Ni at a low temperature lower than or equal to 300° C. (first sintering process) to first form an Ni2Si/poly-Si stacked structure. Then, the Ni metal that has not reacted is removed, and heat treatment at a higher temperature (second sintering process) is carried out to convert the portion of the gate electrode that is in contact with the gate insulating film into NiSi. A full-silicide electrode manufacturing technology is disclosed in the above two-step sintering process.
In this technology, the temperature and time in the first sintering process are adjusted to achieve the state in which the Ni2Si layer 21 containing Ni equal to or more than amount corresponding to Ni necessary to convert the entire gate electrode into NiSi is stacked on part of the remaining gate poly-Si 4 that has not reacted (FIG. 2(a)). This technology is also characterized in that a reaction is initiated between the Ni2Si layer 21 and the remaining poly-Si 4 in the second higher-temperature sintering process so as to convert at least the portion in contact with the gate insulating film into NiSi 15 (FIG. 2(b)). In the above process, the thickness of the Ni2Si film is determined independent of the geometry, such as the gate length, but only by the temperature and time in the first sintering process, so that it is possible to prevent the phenomenon in which the composition of the NiSi electrode unintentionally changes to a Ni-rich composition when the gate length is short.
As described above, the full-silicide metal gate electrode has a controllable effective work function and high compatibility with the CMOS process of relate art, and is applicable onto HfSiON, which is a high dielectric constant gate insulating film. The full silicide metal gate electrode has many advantages which makes it also possible to eliminate the gate length-dependent instability of the NiSi composition (change of the NiSi composition from a desired stoichiometric composition).
The two-step sintering process for eliminating the gate length-dependent instability of the NiSi composition, however, has the following major problems. First, the process margin for temperature and time is small because it is necessary to control the sintering temperature and time to control the thickness of the Ni2Si film formed in the first sintering process. As for the margin for temperature, in particular, the variation in thickness of the Ni2Si film is approximately as large as 20 to 30 nm when the variation in temperature is on the order of 20° C., as described in Symposium on VLSI Technology technical digest, 2005, p. 72. Such variation in film thickness causes variation in element characteristics. Further, as described in the above reference, the interface between the Ni2Si formed in the first sintering process and the poly-Si that has not reacted is not be a flat surface, resulting in generating irregularities ranging from 30 to 50 nm (FIG. 2(c)).
In such circumstances, particularly when the gate length is short, depending on the degree of the irregularities, poly-Si that has not reacted is left after the second sintering process, or no poly-Si that has not reacted is left in the first sintering process and the entire structure is converted into Ni2Si. In either case, the element characteristics could significantly varies.
The variation in element characteristics is particularly significant when the initial height of poly-Si for forming the gate electrode is low. For example, when the initial height of poly-Si for forming the gate electrode is 100 nm, the target thickness values of the Ni2Si film and the remaining poly-Si film that has not reacted need to be 75 to 150 nm and 50 nm or smaller, respectively. However, it is difficult to control the thickness of the remaining poly-Si film to be 50 nm or smaller by taking into consideration of the combined effect of the variation in temperature and the degree of the interface irregularities.
Such problems occur not only when a semiconductor device with an nMOS and a pMOS is manufactured but also when a semiconductor device with only an nMOS or a pMOS is manufactured.